The invention is directed to a method for testing memory modules of the mega-bit generation with arbitrary test patterns in a multi-bit test mode, and to an arrangement for the implementation of this method.
In order to keep testing times short, memory modules of the mega-bit generation comprise a multi-bit test mode in which test information signasl are read-in at the data input of the memory module and simultaneously imaged on a plurality of cells of the cell field. For example, 1M (words).times.1 (bit) -organized memory modules are tested as though they were organized with m cells, such as 256K.times.4, 128K.times.8, 64K.times.16, etc. so that 4, 8, 16 cells, etc. are simultaneously tested with a 1-bit datum per applied memory address.
The data actually written into the respectively m cells depend on the module design of the individual manufacturers. The cell data written-in are the m-dimensional result of the allocation of the one-bit test datum to the individual cells of a cell group described by the m-dimensional function EQU f (DE)={DE}.sub.1, . . . , m with DE.epsilon.{0, 1}
in which DE represents a data information signal that is read into the mega-bit memory module.
The inverse allocation EQU f.sup.-1 ({DA}.sub.1, . . . , m)=DA with DA.epsilon.{0, 1},
is produced upon read-out of the cell contents of a cell group, so that the original test datum again appears at the data output of the memory module having error-free memory cells. DA represents a data information signal that is read out of the mega-bit memory module.
When the negated test datum is written in, the cell data are written into the cells of a cell group negated, so that the negated bit pattern resides in the cell group overall, in comparison to the bit pattern previously written in. The mapping function is: ##EQU1## wherein f.sub.0 and f.sub.1 =f.sub.0 represent the functions prescribed by the module design.
Depending on the module design and, thus manufacturer-dependent, every memory module comprises exactly one mapping function f (DE), proceeding from the test datum, this mapping function generating a defined bit pattern within a cell group. The bit pattern can merely be negated for testing the memory module. However, the memory module is not adequately tested for bit pattern sensitivity with the respectively two bit patterns available. Many errors occur at malfunction cells only when their support field comprises a specific bit pattern. A number of topological tests exist for the recognition of such errors that are based on the interaction of at least two cells, these topological tests working with various test patterns. Topological tests, however, cannot be executed in unlimited fashion in the previous multi-bit test mode because the test patterns needed therefor cannot be generated in the cell fields. They can only be executed in the individual bit mode in mega-bit modules. This, however, is not expedient because the test cycle times are dependent on the type of test and on the storage capacity of the memory module are thus disproportionately high. Test cycle times of up to several hundred hours can occur.